Verilog Continuous Assignment Reg

Posted on | by PHYLICIA P.

{REPLACEMENT-([edit])-()}{REPLACEMENT-(&#;)-()} verilog uninterrupted task reg

/*

module Nonblocking_Assignment (addr1,addr2,wr,din,valid1,valid2,data,aout);

  input [31:0] addr1,addr2;

  input [31:0] din;

  output [31:0] help project valid1,valid2,wr;

  

  reg [31:0] data,aout, addr;

  reg valid;

  

  always @(addr1,addr2,wr,din,valid1,valid2) begin

     applicable <= (valid1 | valid2);

     addr <= (addr1[31:0] | addr2[31:0]);

     info <= (valid & wr) ?

{din[31:2],2'b11} : 32'd0;

     aout <= wr ?

verilog steady paper reg

addr: {addr1[15:0],addr2[31:16]};

  end

  initial

     $monitor($time,"NON-BLOCKING: Attitudes valid1=%b, valid2=%b, wr=%b, addr1=%d, addr2=%d, data=%d, aout=%d", essay regarding having an important drenched county Blocking_Assignment(addr1,addr2,wr,din,valid1,valid2,data,aout);

  input[31:0]addr1,addr2;

  input[31:0]din;

  output[31:0]data,aout;

  input valid1,valid2,wr;

  

  reg[31:0]data,aout,addr;

  reg valid;

  

  [email protected](addr1,addr2,wr,din,valid1,valid2)begin

     valid=(valid1|valid2);

     addr=(addr1[31:0]|addr2[31:0]);

     data=(valid&wr)?{din[31:2],2'b11} : 32'd0;

     aout=wr?addr:{addr1[15:0],addr2[31:16]};

     $monitor($time,"BLOCKING: Figures valid1=%b, valid2=%b, wr=%b, addr1=%d, addr2=%d, data=%d, aout=%d",valid1,valid2,wr,addr1,addr2,data,aout);

  end

endmodule

 

module test;

reg valid1,valid2,wr;

reg[31:0]addr1,addr2,din;

wire[31:0]data,aout;

Blocking_Assignment Block_Assign(addr1,addr2,wr,din,valid1,valid2,data,aout);

//Nonblocking_Assignment Nonblock_Assign(addr1,addr2,wr,din,valid1,valid2,data,aout);

initial begin

  valid1=0;

  valid2=0;

  addr1=32'd12;

  addr2 = 32'd36;

  din=32'd198;

  wr = 1;

  

  #5 valid1 = 1;

  #10 valid1 = 0; valid2 = 1;

  #10 addr1 = 32'd0;addr2=32'd0;

  #5 wr = 0;

  #12 wr = 1;

end

endmodule

 

/*

ncsim> run

                   0NON-BLOCKING: Principles valid1=0, valid2=0, wr=1, addr1=        12, addr2=        36, data=         x aout=         x

                   5NON-BLOCKING: Attitudes valid1=1, valid2=0, wr=1, addr1=        12, addr2=        36, data=         0, aout=        44

                  15NON-BLOCKING: Character valid1=0, valid2=1, wr=1, addr1=        12, addr2=        36, data=       199, aout=        44

                  25NON-BLOCKING: Character valid1=0, valid2=1, wr=1, addr1=         0, addr2=         0, data=       199, aout=        44

                  30NON-BLOCKING: Principles valid1=0, valid2=1, wr=0, addr1=         0, addr2=         0, data=         0, aout=         0

                  42NON-BLOCKING: Figures valid1=0, valid2=1, wr=1, addr1=         0, addr2=         0, data=       199, aout=         0

ncsim: *W,RNQUIE: Simulation is certainly complete.

*/

 

/*

ncsim> run

                   0BLOCKING: Prices valid1=0, valid2=0, wr=1, addr1=        12, addr2=        36, data=         0, aout=        44

                   verilog continual job reg Attitudes valid1=1, valid2=0, wr=1, addr1=        12, addr2=        36, data=       199, aout=        44

                  15BLOCKING: Values valid1=0, valid2=1, wr=1, addr1=        12, addr2=        36, data=       199, aout=        44

                  25BLOCKING: Valuations valid1=0, valid2=1, wr=1, addr1=         0, addr2=         0, data=       199, aout=         0

                  30BLOCKING: Values valid1=0, valid2=1, wr=0, addr1=         0, addr2=         0, data=         0, aout=         0

                  42BLOCKING: Ideals valid1=0, valid2=1, wr=1, addr1=         0, addr2=         0, data=       199, aout=         0

ncsim: *W,RNQUIE: Simulation is complete.

ncsim> exit

*/

{/REPLACEMENT}{/REPLACEMENT}

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